Initial Release
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13
multicore/multicore_fifo_irqs/CMakeLists.txt
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13
multicore/multicore_fifo_irqs/CMakeLists.txt
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add_executable(multicore_fifo_irqs
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multicore_fifo_irqs.c
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)
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target_link_libraries(multicore_fifo_irqs
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pico_multicore
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pico_stdlib)
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# create map/bin/hex file etc.
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pico_add_extra_outputs(multicore_fifo_irqs)
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# add url via pico_set_program_url
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example_auto_set_url(multicore_fifo_irqs)
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76
multicore/multicore_fifo_irqs/multicore_fifo_irqs.c
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76
multicore/multicore_fifo_irqs/multicore_fifo_irqs.c
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/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdio.h>
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#include "pico/stdlib.h"
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#include "pico/multicore.h"
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#include "hardware/irq.h"
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///tag::multicore_fifo_irqs[]
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#define FLAG_VALUE1 123
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#define FLAG_VALUE2 321
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static int core0_rx_val = 0, core1_rx_val = 0;
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void core0_sio_irq() {
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// Just record the latest entry
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while (multicore_fifo_rvalid())
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core0_rx_val = multicore_fifo_pop_blocking();
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multicore_fifo_clear_irq();
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}
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void core1_sio_irq() {
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// Just record the latest entry
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while (multicore_fifo_rvalid())
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core1_rx_val = multicore_fifo_pop_blocking();
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multicore_fifo_clear_irq();
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}
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void core1_entry() {
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multicore_fifo_clear_irq();
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irq_set_exclusive_handler(SIO_IRQ_PROC1, core1_sio_irq);
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irq_set_enabled(SIO_IRQ_PROC1, true);
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// Send something to Core0, this should fire the interrupt.
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multicore_fifo_push_blocking(FLAG_VALUE1);
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while (1)
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tight_loop_contents();
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}
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int main() {
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stdio_init_all();
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printf("Hello, multicore_fifo_irqs!\n");
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// We MUST start the other core before we enabled FIFO interrupts.
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// This is because the launch uses the FIFO's, enabling interrupts before
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// they are used for the launch will result in unexpected behaviour.
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multicore_launch_core1(core1_entry);
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irq_set_exclusive_handler(SIO_IRQ_PROC0, core0_sio_irq);
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irq_set_enabled(SIO_IRQ_PROC0, true);
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// Wait for a bit for things to happen
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sleep_ms(10);
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// Send something back to the other core
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multicore_fifo_push_blocking(FLAG_VALUE2);
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// Wait for a bit for things to happen
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sleep_ms(10);
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printf("Irq handlers should have rx'd some stuff - core 0 got %d, core 1 got %d!\n", core0_rx_val, core1_rx_val);
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while (1)
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tight_loop_contents();
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}
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///end::multicore_fifo_irqs[]
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