diff --git a/adder8.vhd b/adder8.vhd
new file mode 100644
index 0000000..897f4d3
--- /dev/null
+++ b/adder8.vhd
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity adder8 is
+port(	a: in std_logic_vector(7 downto 0);
+		b: in std_logic_vector(7 downto 0);
+		cin: in std_logic;
+		
+		s: out std_logic_vector(7 downto 0);
+		cout: out std_logic
+);
+end adder8;
+
+architecture behav of adder8 is
+
+	signal c: std_logic_vector(8 downto 0);
+	component fulladder
+	port(a, b, cin: in std_logic;
+		 s, cout: out std_logic);
+	end component;
+
+begin
+	
+	c(0) <= cin;
+	
+	ADDERGEN:
+	for i in 7 downto 0 generate
+		fulladderx: fulladder port map
+			(a(i), b(i), c(i), s(i), c(i+1));
+	end generate ADDERGEN;
+	
+	cout <= c(8);
+end;
diff --git a/adder8_tb.vhd b/adder8_tb.vhd
new file mode 100644
index 0000000..e1f8535
--- /dev/null
+++ b/adder8_tb.vhd
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity adder8_tb is
+end adder8_tb;
+
+architecture behav of adder8_tb is
+	
+	component adder8
+		port(	a, b: in std_logic_vector(7 downto 0); cin: in std_logic;
+			 	s: out std_logic_vector(7 downto 0); cout: out std_logic);
+ 	end component;
+ 	
+ 	signal a, b, s: std_logic_vector(7 downto 0);
+ 	signal cin, cout: std_logic;
+ 	
+ begin
+ 	
+ 	uut: adder8 port map(a, b, cin, s, cout);
+ 	
+ 	process
+ 	begin
+ 		
+ 		a <= "01010101";
+ 		b <= "00001111";
+ 		cin <= '0';
+ 		wait for 1 ns;
+ 		
+ 		a <= "11110000";
+ 		b <= "00001111";
+ 		cin <= '1';
+ 		wait for 1 ns;
+ 		
+ 		a <= "00110000";
+ 		b <= "10000110";
+ 		cin <= '0';
+ 		wait for 1 ns;
+ 		
+ 		a <= "00000001";
+ 		b <= "00000001";
+ 		cin <= '1';
+ 		wait for 1 ns;
+ 		
+ 		a <= "11111111";
+ 		b <= "00000100";
+ 		cin <= '1';
+ 		wait for 1 ns;
+ 		
+ 		a <= "11111111";
+ 		b <= "00000101";
+ 		cin <= '0';
+ 		wait for 1 ns;
+ 		
+ 		assert false report "end of test" severity failure;
+ 		
+ 	end process;
+end behav; 
\ No newline at end of file
diff --git a/buzzer.vhd b/buzzer.vhd
new file mode 100644
index 0000000..a81bfa7
--- /dev/null
+++ b/buzzer.vhd
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity buzzer is
+port(	i: in std_logic_vector(7 downto 0);
+		o: out std_logic
+);
+end buzzer;
+
+--reduced with Quine-McCluskey
+--inputs outside 1-100 are don't-cares
+architecture behav of buzzer is
+	signal A, B, C, D, E, F, G: std_logic;
+	signal T: std_logic_vector(19 downto 0);
+begin
+	A <= i(0);
+	B <= i(1);
+	C <= i(2);
+	D <= i(3);
+	E <= i(4);
+	F <= i(5);
+	G <= i(6);
+	
+	o <= T(0) or T(1) or T(2) or T(3) or T(4) or T(5) or T(6) or T(7) or T(8) or T(9) or T(10) or T(11) or T(12) or T(13) or T(14) or T(15) or T(16) or T(17) or T(18) or T(19);
+	
+	T(0) <= A and not B and C and not D and not E and not F and not G;
+	T(1) <= not A and B and not C and D and not E and not F and not G;
+	T(2) <= A and B and C and D and not E and not F and not G;
+	T(3) <= not A and not B and C and not D and E and not F and not G;
+	T(4) <= A and not B and not C and D and E and not F and not G;
+	T(5) <= not A and B and C and D and E and not F and not G;
+	T(6) <= A and B and not C and not D and not E and F and not G;
+	T(7) <= not A and not B and not C and D and not E and F;
+	T(8) <= A and not B and C and D and not E and F;
+	T(9) <= not A and B and not C and not D and E and F;
+	T(10) <= A and B and C and not D and E and F;
+	T(11) <= not A and not B and C and D and E and F;
+	T(12) <= A and not B and not C and not D and not E and not F and G;
+	T(13) <= not A and B and C and not D and not E and G;
+	T(14) <= A and B and not C and D and not E and G;
+	T(15) <= not A and not B and not C and not D and E and G;
+	T(16) <= A and not B and C and not D and E and G;
+	T(17) <= not A and B and not C and D and E and G;
+	T(18) <= A and B and C and D and E and G;
+	T(19) <= C and F and G;
+	
+end behav;
diff --git a/buzzer_tb.vhd b/buzzer_tb.vhd
new file mode 100644
index 0000000..d32d7ea
--- /dev/null
+++ b/buzzer_tb.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity buzzer_tb is
+end buzzer_tb;
+
+architecture behav of buzzer_tb is
+
+	component buzzer
+		port( i: in std_logic_vector(7 downto 0); o: out std_logic);
+	end component;
+
+	signal counter: integer := 1;
+	signal asvector: std_logic_vector(7 downto 0);
+	signal outpt: std_logic;
+	
+begin
+	
+	asvector <= std_logic_vector(to_unsigned(counter, 8));
+	buzzer_0: buzzer port map (asvector, outpt);
+	
+	process
+	begin
+		while (counter <= 100) loop
+			--report integer'image(counter);
+			wait for 1 ns;
+			counter <= counter + 1;
+		end loop;
+		--assert false report "end of test" severity failure;
+		wait;
+	end process;
+end behav;
diff --git a/comparator8.vhd b/comparator8.vhd
new file mode 100644
index 0000000..4301364
--- /dev/null
+++ b/comparator8.vhd
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comparator8 is
+	port(	a: in std_logic_vector(7 downto 0);
+			b: in std_logic_vector(7 downto 0);
+			
+			o: out std_logic
+	);
+end comparator8;
+
+architecture behav of comparator8 is
+begin
+	o <= (a(0) xnor b(0)) and (a(1) xnor b(1)) and (a(2) xnor b(2)) and (a(3) xnor b(3)) and (a(4) xnor b(4)) and (a(5) xnor b(5)) and (a(6) xnor b(6)) and (a(7) xnor b(7));
+end behav;
\ No newline at end of file
diff --git a/counter8.vhd b/counter8.vhd
new file mode 100644
index 0000000..34d9554
--- /dev/null
+++ b/counter8.vhd
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity counter8 is
+port(	clk: in std_logic;
+		rst: in std_logic;
+		
+		q: out std_logic_vector(7 downto 0)
+);
+end counter8;
+
+architecture behav of counter8 is
+	
+	signal crnt: std_logic_vector(7 downto 0);
+	--signal iter: std_logic_vector(7 downto 0);
+	signal nex: std_logic_vector(7 downto 0);
+	
+	component dff
+	port(	d, clk, rst: in std_logic;
+			q: out std_logic);
+	end component;
+	
+	component adder8
+	port(	a, b: in std_logic_vector(7 downto 0);
+			cin: in std_logic;
+			s: out std_logic_vector(7 downto 0);
+			cout: out std_logic);
+	end component;
+	
+	--component mux8
+	--port(	a, b: in std_logic_vector(7 downto 0);
+	--		s: in std_logic;
+	--		y: out std_logic_vector(7 downto 0));
+	--end component;
+begin
+
+	--resetter: mux8 port map(00000000, iter, rst, nex);
+	iterator: adder8 port map(crnt, "00000000", '1', nex, open);
+	
+	q <= crnt;
+	 
+	DFFGEN:
+	for i in 7 downto 0 generate
+		dffx: dff port map
+			(nex(i), clk, rst, crnt(i));
+	end generate DFFGEN;
+end;
diff --git a/counter8_tb.vhd b/counter8_tb.vhd
new file mode 100644
index 0000000..3c6d9f7
--- /dev/null
+++ b/counter8_tb.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity counter8_tb is
+end counter8_tb;
+
+architecture behav of counter8_tb is
+	
+	component counter8
+		port( clk, rst: in std_logic; q: out std_logic_vector(7 downto 0));
+	end component;
+	
+	signal clk, rst: std_logic := '1';
+	signal outpt: std_logic_vector(7 downto 0);
+
+begin
+	
+	clk <= not clk after 500 ps;
+	
+	uut: counter8 port map(clk, rst, outpt);
+	
+	process
+	begin
+		rst <= '0';
+		wait for 3 ns;
+		rst <= '1';
+		wait for 300 ns;
+		assert false report "end of test" severity failure;
+	end process;
+end behav;
diff --git a/dff.vhd b/dff.vhd
new file mode 100644
index 0000000..f463c6f
--- /dev/null
+++ b/dff.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity dff is
+port(	d: in std_logic;
+		clk: in std_logic;
+		rst: in std_logic;
+		
+		q: out std_logic
+);
+end dff;
+
+architecture behav of dff is
+begin
+	process (clk) is
+	begin
+		if rising_edge(clk) then
+			q <= d and rst;
+		end if;
+	end process;
+end behav;
diff --git a/dff_tb.vhd b/dff_tb.vhd
new file mode 100644
index 0000000..cde77c2
--- /dev/null
+++ b/dff_tb.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff_tb is
+end dff_tb;
+
+architecture behav of dff_tb is
+	
+	component dff
+		port( d, clk, rst: in std_logic; q: out std_logic);
+	end component;
+	
+	signal d: std_logic := '1';
+	signal clk, rst: std_logic := '1';
+	signal q: std_logic;
+	
+begin
+	
+	clk <= not clk after 500 ps;
+	uut: dff port map(d, clk, rst, q);
+	
+	process
+	begin
+		wait for 3 ns;
+		rst <= '0';
+		wait for 3 ns;
+		rst <= '1';
+		wait for 2 ns;
+		d <= '0';
+		wait for 2 ns;
+		d <= '1';
+		wait for 2 ns;
+		d <= '0';
+		wait for 2 ns;
+		assert false report "end of test" severity failure;
+	end process;
+end behav;
diff --git a/fizzbuzz.vhd b/fizzbuzz.vhd
new file mode 100644
index 0000000..9ebb79b
--- /dev/null
+++ b/fizzbuzz.vhd
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fizzbuzz is
+	port(	clk: in std_logic;
+			rst: in std_logic;
+			
+			fizz: out std_logic;
+			buzz: out std_logic;
+			num: out std_logic;
+			number: out std_logic_vector(7 downto 0)
+	);
+end fizzbuzz;
+
+architecture behav of fizzbuzz is
+	
+	component counter8
+	port( clk, rst: in std_logic; q: out std_logic_vector(7 downto 0));
+	end component;
+	
+	component fizzer
+	port( i: in std_logic_vector(7 downto 0); o: out std_logic);
+	end component;
+	
+	component buzzer
+	port( i: in std_logic_vector(7 downto 0); o: out std_logic);
+	end component;
+	
+	component mux2
+	port( a, b, s: in std_logic; q: out std_logic);
+	end component;
+	
+	component mux8
+	port( a, b: in std_logic_vector(7 downto 0); s: in std_logic; y: out std_logic_vector(7 downto 0));
+	end component;
+	
+	component dff
+	port( d, clk, rst: in std_logic; q: out std_logic);
+	end component;
+	
+	component comparator8
+	port(a, b: in std_logic_vector(7 downto 0); o: out std_logic);
+	end component;
+	
+	signal count: std_logic_vector(7 downto 0);
+	signal fizzout, buzzout: std_logic;
+	signal ishundred: std_logic;
+	signal disabled: std_logic;
+	signal dffin: std_logic;
+	signal numsig: std_logic;
+	signal fizzsig: std_logic;
+	signal buzzsig: std_logic;
+	
+begin
+	
+	dffin <= disabled or ishundred;
+	numsig <=  not (fizzsig or buzzsig or disabled);
+	num <= numsig;
+	fizz <= fizzsig;
+	buzz <= buzzsig;
+	
+	disabler: dff port map(dffin, clk, rst, disabled);
+	cntr: counter8 port map(clk, rst, count);
+	fizzer_0: fizzer port map(count, fizzout);
+	buzzer_0: buzzer port map(count, buzzout);
+	numblanker: mux8 port map("00000000", count, numsig, number);
+	fizzmux: mux2 port map(fizzout, '0', disabled, fizzsig);
+	buzzmux: mux2 port map(buzzout, '0', disabled, buzzsig);
+	comp: comparator8 port map(count, "01100100", ishundred);
+	
+end behav;
+	
\ No newline at end of file
diff --git a/fizzbuzz_tb.vhd b/fizzbuzz_tb.vhd
new file mode 100644
index 0000000..d947b36
--- /dev/null
+++ b/fizzbuzz_tb.vhd
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fizzbuzz_tb is
+end fizzbuzz_tb;
+
+architecture behav of fizzbuzz_tb is
+	
+	component fizzbuzz
+		port( clk, rst: in std_logic; fizz, buzz, num: out std_logic; number: out std_logic_vector(7 downto 0));
+	end component;
+	
+	--signal cnt: integer := 1;
+	signal clk: std_logic := '1';
+	signal rst: std_logic := '1';
+	signal fizz, buzz, num: std_logic;
+	signal number: std_logic_vector(7 downto 0);
+	
+begin
+	
+	clk <= not clk after 500 ps;
+	
+	fb: fizzbuzz port map(clk, rst, fizz, buzz, num, number);
+	
+	process
+	begin
+		rst <= '0';
+		wait for 5500 ps;
+		rst <= '1';
+		wait for 110 ns;
+		--wait;
+		assert false report "end of test" severity failure;
+	end process;
+	
+end behav;
diff --git a/fizzer.vhd b/fizzer.vhd
new file mode 100644
index 0000000..422e4a4
--- /dev/null
+++ b/fizzer.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fizzer is
+port(	i: in std_logic_vector(7 downto 0);
+		o: out std_logic
+);
+end fizzer;
+
+--reduced with Quine-McCluskey
+--inputs outside 1-100 are don't-cares
+architecture behav of fizzer is
+	signal A, B, C, D, E, F, G: std_logic;
+	signal T: std_logic_vector(32 downto 0);
+begin
+	A <= i(0);
+	B <= i(1);
+	C <= i(2);
+	D <= i(3);
+	E <= i(4);
+	F <= i(5);
+	G <= i(6);
+	
+	o <= T(0) or T(1) or T(2) or T(3) or T(4) or T(5) or T(6) or T(7) or T(8) or T(9) or T(10) or T(11) or T(12) or T(13) or T(14) or T(15) or T(16) or T(17) or T(18) or T(19) or T(20) or T(21) or T(22) or T(23) or T(24) or T(25) or T(26) or T(27) or T(28) or T(29) or T(30) or T(31) or T(32);
+	
+	T(0) <= A  and B and not C and not D and not E and not F and not G;
+	T(1) <= not A  and B and C and not D and not E and not F and not G;
+	T(2) <= A  and not B and not C and D and not E and not F and not G;
+	T(3) <= not A  and not B and C and D and not E and not F and not G;
+	T(4) <= A  and B and C and D and not E and not F and not G;
+	T(5) <= not A  and B and not C and not D and E and not F and not G;
+	T(6) <= A  and not B and C and not D and E and not F and not G;
+	T(7) <= not A  and not B and not C and D and E and not F and not G;
+	T(8) <= A  and B and not C and D and E and not F and not G;
+	T(9) <= not A  and B and C and D and E and not F and not G;
+	T(10) <= A  and not B and not C and not D and not E and F and not G;
+	T(11) <= not A  and not B and C and not D and not E and F and not G;
+	T(12) <= A  and B and C and not D and not E and F;
+	T(13) <= not A  and B and not C and D and not E and F;
+	T(14) <= A  and not B and C and D and not E and F;
+	T(15) <= not A  and not B and not C and not D and E and F;
+	T(16) <= A  and B and not C and not D and E and F;
+	T(17) <= not A  and B and C and not D and E and F;
+	T(18) <= A  and not B and not C and D and E and F;
+	T(19) <= not A  and not B and C and D and E and F;
+	T(20) <= A  and B and C and D and E and F;
+	T(21) <= not A  and B and not C and not D and not E and not F and G;
+	T(22) <= A  and not B and C and not D and not E and G;
+	T(23) <= not A  and not B and not C and D and not E and G;
+	T(24) <= A  and B and not C and D and not E and G;
+	T(25) <= not A  and B and C and D and not E and G;
+	T(26) <= A  and not B and not C and not D and E and G;
+	T(27) <= not A  and not B and C and not D and E and G;
+	T(28) <= A  and B and C and not D and E and G;
+	T(29) <= not A  and B and not C and D and E and G;
+	T(30) <= A  and not B and C and D and E and G;
+	T(31) <= not A  and not B and not C and F and G;
+	T(32) <= A  and B and F and G;
+	
+end behav;
diff --git a/fizzer_tb.vhd b/fizzer_tb.vhd
new file mode 100644
index 0000000..3a48cb0
--- /dev/null
+++ b/fizzer_tb.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fizzer_tb is
+end fizzer_tb;
+
+architecture behav of fizzer_tb is
+
+	component fizzer
+		port( i: in std_logic_vector(7 downto 0); o: out std_logic);
+	end component;
+
+	signal counter: integer := 1;
+	signal asvector: std_logic_vector(7 downto 0);
+	signal outpt: std_logic;
+	
+begin
+	
+	asvector <= std_logic_vector(to_unsigned(counter, 8));
+	fizzer_0: fizzer port map (asvector, outpt);
+	
+	process
+	begin
+		while (counter <= 100) loop
+			--report integer'image(counter);
+			wait for 1 ns;
+			counter <= counter + 1;
+		end loop;
+		--assert false report "end of test" severity failure;
+		wait;
+	end process;
+end behav;
diff --git a/fulladder.vhd b/fulladder.vhd
new file mode 100644
index 0000000..a2ea27b
--- /dev/null
+++ b/fulladder.vhd
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity fulladder is
+port(	a: in std_logic;
+		b: in std_logic;
+		cin: in std_logic;
+		
+		s: out std_logic;
+		cout: out std_logic
+);
+end fulladder;
+
+architecture behav of fulladder is
+begin
+	cout <= (a and b) or (a and cin) or (b and cin);
+	s <= a xor b xor cin;
+end behav;
diff --git a/mux2.vhd b/mux2.vhd
new file mode 100644
index 0000000..3e28dca
--- /dev/null
+++ b/mux2.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mux2 is
+	port(	a: in std_logic;
+			b: in std_logic;
+			s: in std_logic;
+			
+			q: out std_logic
+	);
+end mux2;
+
+architecture behav of mux2 is
+begin
+	q <= (a and not s) or (b and s);
+end behav;
diff --git a/mux8.vhd b/mux8.vhd
new file mode 100644
index 0000000..d507ef0
--- /dev/null
+++ b/mux8.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity mux8 is
+port(	a: in std_logic_vector(7 downto 0);
+		b: in std_logic_vector(7 downto 0);
+		s: in std_logic;
+		
+		y: out std_logic_vector(7 downto 0)
+);
+end mux8;
+
+architecture behav of mux8 is
+begin
+	y(7) <= (a(7) and not s) or (b(7) and s);
+	y(6) <= (a(6) and not s) or (b(6) and s);
+	y(5) <= (a(5) and not s) or (b(5) and s);
+	y(4) <= (a(4) and not s) or (b(4) and s);
+	y(3) <= (a(3) and not s) or (b(3) and s);
+	y(2) <= (a(2) and not s) or (b(2) and s);
+	y(1) <= (a(1) and not s) or (b(1) and s);
+	y(0) <= (a(0) and not s) or (b(0) and s);
+end;
+ 
\ No newline at end of file