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23 lines
322 B
VHDL
23 lines
322 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity dff is
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port( d: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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q: out std_logic
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);
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end dff;
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architecture behav of dff is
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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q <= d and rst;
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end if;
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end process;
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end behav;
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