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38 lines
658 B
VHDL
38 lines
658 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity dff_tb is
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end dff_tb;
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architecture behav of dff_tb is
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component dff
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port( d, clk, rst: in std_logic; q: out std_logic);
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end component;
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signal d: std_logic := '1';
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signal clk, rst: std_logic := '1';
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signal q: std_logic;
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begin
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clk <= not clk after 500 ps;
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uut: dff port map(d, clk, rst, q);
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process
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begin
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wait for 3 ns;
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rst <= '0';
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wait for 3 ns;
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rst <= '1';
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wait for 2 ns;
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d <= '0';
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wait for 2 ns;
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d <= '1';
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wait for 2 ns;
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d <= '0';
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wait for 2 ns;
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assert false report "end of test" severity failure;
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end process;
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end behav;
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