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36 lines
753 B
VHDL
36 lines
753 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity fizzbuzz_tb is
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end fizzbuzz_tb;
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architecture behav of fizzbuzz_tb is
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component fizzbuzz
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port( clk, rst: in std_logic; fizz, buzz, num: out std_logic; number: out std_logic_vector(7 downto 0));
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end component;
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--signal cnt: integer := 1;
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signal clk: std_logic := '1';
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signal rst: std_logic := '1';
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signal fizz, buzz, num: std_logic;
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signal number: std_logic_vector(7 downto 0);
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begin
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clk <= not clk after 500 ps;
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fb: fizzbuzz port map(clk, rst, fizz, buzz, num, number);
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process
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begin
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rst <= '0';
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wait for 5500 ps;
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rst <= '1';
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wait for 110 ns;
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--wait;
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assert false report "end of test" severity failure;
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end process;
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end behav;
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