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20 lines
336 B
VHDL
20 lines
336 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity fulladder is
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port( a: in std_logic;
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b: in std_logic;
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cin: in std_logic;
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s: out std_logic;
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cout: out std_logic
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);
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end fulladder;
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architecture behav of fulladder is
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begin
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cout <= (a and b) or (a and cin) or (b and cin);
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s <= a xor b xor cin;
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end behav;
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