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15 lines
432 B
VHDL
15 lines
432 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity comparator8 is
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port( a: in std_logic_vector(7 downto 0);
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b: in std_logic_vector(7 downto 0);
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o: out std_logic
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);
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end comparator8;
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architecture behav of comparator8 is
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begin
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o <= (a(0) xnor b(0)) and (a(1) xnor b(1)) and (a(2) xnor b(2)) and (a(3) xnor b(3)) and (a(4) xnor b(4)) and (a(5) xnor b(5)) and (a(6) xnor b(6)) and (a(7) xnor b(7));
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end behav; |