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48 lines
1.0 KiB
VHDL
48 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity counter8 is
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port( clk: in std_logic;
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rst: in std_logic;
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q: out std_logic_vector(7 downto 0)
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);
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end counter8;
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architecture behav of counter8 is
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signal crnt: std_logic_vector(7 downto 0);
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--signal iter: std_logic_vector(7 downto 0);
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signal nex: std_logic_vector(7 downto 0);
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component dff
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port( d, clk, rst: in std_logic;
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q: out std_logic);
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end component;
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component adder8
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port( a, b: in std_logic_vector(7 downto 0);
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cin: in std_logic;
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s: out std_logic_vector(7 downto 0);
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cout: out std_logic);
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end component;
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--component mux8
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--port( a, b: in std_logic_vector(7 downto 0);
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-- s: in std_logic;
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-- y: out std_logic_vector(7 downto 0));
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--end component;
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begin
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--resetter: mux8 port map(00000000, iter, rst, nex);
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iterator: adder8 port map(crnt, "00000000", '1', nex, open);
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q <= crnt;
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DFFGEN:
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for i in 7 downto 0 generate
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dffx: dff port map
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(nex(i), clk, rst, crnt(i));
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end generate DFFGEN;
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end;
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