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https://github.com/Ikatono/vhdlFizzBuzz.git
synced 2025-10-29 04:56:12 -05:00
72 lines
1.9 KiB
VHDL
72 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity fizzbuzz is
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port( clk: in std_logic;
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rst: in std_logic;
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fizz: out std_logic;
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buzz: out std_logic;
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num: out std_logic;
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number: out std_logic_vector(7 downto 0)
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);
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end fizzbuzz;
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architecture behav of fizzbuzz is
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component counter8
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port( clk, rst: in std_logic; q: out std_logic_vector(7 downto 0));
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end component;
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component fizzer
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port( i: in std_logic_vector(7 downto 0); o: out std_logic);
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end component;
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component buzzer
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port( i: in std_logic_vector(7 downto 0); o: out std_logic);
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end component;
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component mux2
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port( a, b, s: in std_logic; q: out std_logic);
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end component;
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component mux8
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port( a, b: in std_logic_vector(7 downto 0); s: in std_logic; y: out std_logic_vector(7 downto 0));
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end component;
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component dff
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port( d, clk, rst: in std_logic; q: out std_logic);
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end component;
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component comparator8
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port(a, b: in std_logic_vector(7 downto 0); o: out std_logic);
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end component;
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signal count: std_logic_vector(7 downto 0);
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signal fizzout, buzzout: std_logic;
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signal ishundred: std_logic;
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signal disabled: std_logic;
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signal dffin: std_logic;
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signal numsig: std_logic;
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signal fizzsig: std_logic;
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signal buzzsig: std_logic;
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begin
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dffin <= disabled or ishundred;
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numsig <= not (fizzsig or buzzsig or disabled);
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num <= numsig;
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fizz <= fizzsig;
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buzz <= buzzsig;
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disabler: dff port map(dffin, clk, rst, disabled);
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cntr: counter8 port map(clk, rst, count);
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fizzer_0: fizzer port map(count, fizzout);
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buzzer_0: buzzer port map(count, buzzout);
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numblanker: mux8 port map("00000000", count, numsig, number);
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fizzmux: mux2 port map(fizzout, '0', disabled, fizzsig);
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buzzmux: mux2 port map(buzzout, '0', disabled, buzzsig);
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comp: comparator8 port map(count, "01100100", ishundred);
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end behav;
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