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31 lines
586 B
VHDL
31 lines
586 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity counter8_tb is
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end counter8_tb;
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architecture behav of counter8_tb is
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component counter8
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port( clk, rst: in std_logic; q: out std_logic_vector(7 downto 0));
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end component;
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signal clk, rst: std_logic := '1';
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signal outpt: std_logic_vector(7 downto 0);
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begin
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clk <= not clk after 500 ps;
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uut: counter8 port map(clk, rst, outpt);
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process
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begin
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rst <= '0';
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wait for 3 ns;
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rst <= '1';
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wait for 300 ns;
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assert false report "end of test" severity failure;
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end process;
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end behav;
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