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35 lines
629 B
VHDL
35 lines
629 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity adder8 is
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port( a: in std_logic_vector(7 downto 0);
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b: in std_logic_vector(7 downto 0);
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cin: in std_logic;
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s: out std_logic_vector(7 downto 0);
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cout: out std_logic
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);
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end adder8;
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architecture behav of adder8 is
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signal c: std_logic_vector(8 downto 0);
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component fulladder
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port(a, b, cin: in std_logic;
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s, cout: out std_logic);
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end component;
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begin
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c(0) <= cin;
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ADDERGEN:
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for i in 7 downto 0 generate
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fulladderx: fulladder port map
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(a(i), b(i), c(i), s(i), c(i+1));
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end generate ADDERGEN;
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cout <= c(8);
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end;
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