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17 lines
259 B
VHDL
17 lines
259 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity mux2 is
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port( a: in std_logic;
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b: in std_logic;
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s: in std_logic;
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q: out std_logic
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);
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end mux2;
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architecture behav of mux2 is
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begin
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q <= (a and not s) or (b and s);
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end behav;
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