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25 lines
624 B
VHDL
25 lines
624 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity mux8 is
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port( a: in std_logic_vector(7 downto 0);
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b: in std_logic_vector(7 downto 0);
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s: in std_logic;
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y: out std_logic_vector(7 downto 0)
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);
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end mux8;
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architecture behav of mux8 is
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begin
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y(7) <= (a(7) and not s) or (b(7) and s);
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y(6) <= (a(6) and not s) or (b(6) and s);
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y(5) <= (a(5) and not s) or (b(5) and s);
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y(4) <= (a(4) and not s) or (b(4) and s);
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y(3) <= (a(3) and not s) or (b(3) and s);
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y(2) <= (a(2) and not s) or (b(2) and s);
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y(1) <= (a(1) and not s) or (b(1) and s);
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y(0) <= (a(0) and not s) or (b(0) and s);
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end;
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